1. Field
Example embodiments are directed a semiconductor device and methods of manufacturing and operating the same, and more particularly, to a capacitorless dynamic random access memory (DRAM) and methods of manufacturing and operating the same.
2. Description of Related Art
A memory cell of a conventional dynamic random access memory (DRAM), may have a 1T/1C structure including one transistor and one capacitor. It may be difficult to reduce a cell area of the conventional DRAM including both the transistor and the capacitor.
In order to scale down conventional DRAMs, a DRAM that may store data with a transistor and without a capacitor, that is, a capacitorless 1T DRAM, has been suggested. The capacitorless 1T DRAM, hereinafter referred to as a conventional capacitorless DRAM, may include a channel that is electrically floated.
FIG. 1 illustrates a conventional capacitorless DRAM.
Referring to FIG. 1, a gate 200 may be formed on a silicon-on-insulator (SOI) substrate 100 that has a structure in which a first silicon layer 10, an oxide layer 20, and a second silicon layer 30 are sequentially stacked. The gate 200 may be formed of a gate insulating layer 40 and a gate conductive layer 50 sequentially stacked on the second silicon layer 30. A source 30a and a drain 30b may be formed in the second silicon layer 30 on both sides of the gate 200. The source 30a and the drain 30b of the second silicon layer 30 may be silicon layers doped with n-type impurities of high density. A floating channel body 30c that is electrically separated from the first silicon layer 10 by the oxide layer 20 may be formed between the source 30a and the drain 30b. The floating channel body 30c may be a p-type silicon layer and may function as data storage. Because the floating channel body 30c may display different electric resistances in a state of the floating channel body 30c where excess holes are accumulated (hereinafter, a first state) and a state where no excess holes are accumulated (hereinafter, a second state), the first and second states may correspond to data ‘1’ and ‘0’, respectively.
However, the data retention characteristics of the floating channel body 30c in the conventional capacitorless DRAM may not be desirable. For example, because a broad area of the floating channel body 30c contacts with the source 30a and the drain 30b in the conventional capacitorless DRAM, charges may leak at the junction areas therebetween. Accordingly, the data retention time in the floating channel body 30c may be reduced.
In addition, since the conventional capacitorless DRAM is formed on the expensive SOI substrate 100, increased manufacturing costs may be incurred.